Familiarity with Tanner L-EDIT EDA Tools: To study the main features and utilities of the tools for design and physical design of circuits. Report the pros and cons of the tool.
To find dc and transient response of a CMOS Inverter Circuit and its Physical Design using minimum dimension criteria. Hence extract various design parameters from simulation results.
To simulate transient response of CMOS NAND Gate (Fig.1). Physical Design the logic gate or design the layout, using minimum dimension criteria.
Simulate firstly minimum dimension CMOS inverter circuit using SPICE. Hence analyze and plot power and delay variations i) with voltage scaling, ii) For dimension, load and frequency variations.
Simulate CMOS NAND, NOR and XOR circuits using SPICE. Hence analyze and plot their power and delay variations i)with voltage scaling, ii)For dimension, load and frequency variations.
Design a differential amplifier circuit for a voltage gain of 10. Design its layout.
Physical Design of a complex circuit AOI/ OAI, making layout using Euler’s method, for delay, power and area centric designs.
Design a four input CMOS NAND and NOR gates with the constraint propagation delay not exceeding 10ns. Compare LVS.
Familiarity with Cadence Familiarization with Cadence EDA Tools. To study the main features and utilities of the tools for design and physical layout design. Report the same in practical file.
Design NAND NOR, XOR circuits using Cadence EDA Tools, for delay and power centric design criteria.
Physical design a full adder circuit using minimum number of CMOS NAND gates.
Design triangular wave generator using OP-Amps in SPICE.
Familiarization with COMSOL Multiphysics Tool and its applications for Design and study of 1D Heat Transfer with Radiation model
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